The present invention relates to a circuit arrangement wherein two or more semiconductor chips are electrically connected in parallel in order to be able to process higher load currents. The parallel connection is usually carried out, inter alia, by means of one or a plurality of bonding wires routed completely or substantially (e.g., by conductor track support points which are situated between adjacent semiconductor chips and to which the bonding wires are bonded)—optionally from chip top side to chip top side. Rapid changes in the load current such as those occurring during switching processes, for example, can lead to undesirably high induced voltages on account of unavoidable inductances of the bonding wires and other electrical connection conductors of the semiconductor chips connected in parallel. This holds true particularly if a large number of semiconductor chips are intended to be connected in parallel. By way of example, semiconductor chips based on the basic semiconductor material silicon carbide (SiC) or gallium nitride (GaN) are often manufactured with a small basic chip area in order to avoid losses of yield. This has the consequence that, in order to obtain a desired current-carrying capacity of the circuit arrangement, a large number of semiconductor chips operated synchronously must be connected in parallel since the current-carrying capacity of semiconductor chips decreases as the basic chip area decreases (for an identical or similar chip construction). In general, however, the arrangement of many chips and associated connection lines results in a high leakage inductance and asymmetrical operation of the semiconductor chips of a parallel connection in the sense that the load currents of different semiconductor chips of the parallel connection differ significantly.
One measure for keeping down the inductance of such a parallel connection consists of arranging the parallel-connected semiconductor chips in a series that runs perpendicular to the main current direction of the circuit arrangement. In the case of small semiconductor chips (basic area less than or equal to 40 mm2, less than or equal to 25 mm2 or less than or equal to 10 mm2), achieving a high current intensity (e.g., 400 A to 3000 A or higher) necessitates a very high number of semiconductor chips to be connected in parallel, for example IGBTs, which are connected in parallel and are operated simultaneously with identical switching states. In the example with the IGBTs connected in parallel, freewheeling diodes with respect to the IGBTs should not be regarded as “connected in parallel with the IGBTs” since they are not operated simultaneously with the IGBTs with identical switching states. If all the semiconductor chips to be connected in parallel were arranged in a series, this would result in a very short power semiconductor module having an extremely large width, but this is not always attractive because it contravenes geometrical boundary conditions of the devices.